PIC18LF26K22 |
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CONFIG1H (address:0x300001, mask:0x25) |
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FOSC -- Oscillator Selection bits |
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FOSC = LP |
0xF0 |
LP oscillator. |
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FOSC = XT |
0xF1 |
XT oscillator. |
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FOSC = HSHP |
0xF2 |
HS oscillator (high power > 16 MHz). |
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FOSC = HSMP |
0xF3 |
HS oscillator (medium power 4-16 MHz). |
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FOSC = ECHP |
0xF4 |
EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz). |
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FOSC = ECHPIO6 |
0xF5 |
EC oscillator (high power, >16 MHz). |
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FOSC = RC |
0xF6 |
External RC oscillator, CLKOUT function on OSC2. |
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FOSC = RCIO6 |
0xF7 |
External RC oscillator. |
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FOSC = INTIO67 |
0xF8 |
Internal oscillator block. |
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FOSC = INTIO7 |
0xF9 |
Internal oscillator block, CLKOUT function on OSC2. |
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FOSC = ECMP |
0xFA |
EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz). |
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FOSC = ECMPIO6 |
0xFB |
EC oscillator (medium power, 500 kHz-16 MHz). |
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FOSC = ECLP |
0xFC |
EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz). |
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FOSC = ECLPIO6 |
0xFD |
EC oscillator (low power, <500 kHz). |
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PLLCFG -- 4X PLL Enable |
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PLLCFG = OFF |
0xEF |
Oscillator used directly. |
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PLLCFG = ON |
0xFF |
Oscillator multiplied by 4. |
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PRICLKEN -- Primary clock enable bit |
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PRICLKEN = OFF |
0xDF |
Primary clock can be disabled by software. |
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PRICLKEN = ON |
0xFF |
Primary clock enabled. |
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FCMEN -- Fail-Safe Clock Monitor Enable bit |
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FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
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FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
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IESO -- Internal/External Oscillator Switchover bit |
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IESO = OFF |
0x7F |
Oscillator Switchover mode disabled. |
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IESO = ON |
0xFF |
Oscillator Switchover mode enabled. |
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CONFIG2L (address:0x300002, mask:0x1F) |
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PWRTEN -- Power-up Timer Enable bit |
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PWRTEN = ON |
0xFE |
Power up timer enabled. |
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PWRTEN = OFF |
0xFF |
Power up timer disabled. |
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BOREN -- Brown-out Reset Enable bits |
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BOREN = OFF |
0xF9 |
Brown-out Reset disabled in hardware and software. |
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BOREN = ON |
0xFB |
Brown-out Reset enabled and controlled by software (SBOREN is enabled). |
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BOREN = NOSLP |
0xFD |
Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled). |
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BOREN = SBORDIS |
0xFF |
Brown-out Reset enabled in hardware only (SBOREN is disabled). |
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BORV -- Brown Out Reset Voltage bits |
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BORV = 285 |
0xE7 |
VBOR set to 2.85 V nominal. |
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BORV = 250 |
0xEF |
VBOR set to 2.50 V nominal. |
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BORV = 220 |
0xF7 |
VBOR set to 2.20 V nominal. |
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BORV = 190 |
0xFF |
VBOR set to 1.90 V nominal. |
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CONFIG2H (address:0x300003, mask:0x3F) |
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WDTEN -- Watchdog Timer Enable bits |
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WDTEN = OFF |
0xFC |
Watch dog timer is always disabled. SWDTEN has no effect. |
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WDTEN = NOSLP |
0xFD |
WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect. |
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WDTEN = SWON |
0xFE |
WDT is controlled by SWDTEN bit of the WDTCON register. |
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WDTEN = ON |
0xFF |
WDT is always enabled. SWDTEN bit has no effect. |
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WDTPS -- Watchdog Timer Postscale Select bits |
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WDTPS = 1 |
0xC3 |
1:1. |
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WDTPS = 2 |
0xC7 |
1:2. |
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WDTPS = 4 |
0xCB |
1:4. |
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WDTPS = 8 |
0xCF |
1:8. |
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WDTPS = 16 |
0xD3 |
1:16. |
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WDTPS = 32 |
0xD7 |
1:32. |
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WDTPS = 64 |
0xDB |
1:64. |
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WDTPS = 128 |
0xDF |
1:128. |
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WDTPS = 256 |
0xE3 |
1:256. |
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WDTPS = 512 |
0xE7 |
1:512. |
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WDTPS = 1024 |
0xEB |
1:1024. |
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WDTPS = 2048 |
0xEF |
1:2048. |
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WDTPS = 4096 |
0xF3 |
1:4096. |
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WDTPS = 8192 |
0xF7 |
1:8192. |
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WDTPS = 16384 |
0xFB |
1:16384. |
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WDTPS = 32768 |
0xFF |
1:32768. |
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CONFIG3H (address:0x300005, mask:0xBF) |
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CCP2MX -- CCP2 MUX bit |
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CCP2MX = PORTB3 |
0xFE |
CCP2 input/output is multiplexed with RB3. |
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CCP2MX = PORTC1 |
0xFF |
CCP2 input/output is multiplexed with RC1. |
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PBADEN -- PORTB A/D Enable bit |
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PBADEN = OFF |
0xFD |
PORTB<5:0> pins are configured as digital I/O on Reset. |
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PBADEN = ON |
0xFF |
PORTB<5:0> pins are configured as analog input channels on Reset. |
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CCP3MX -- P3A/CCP3 Mux bit |
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CCP3MX = PORTC6 |
0xFB |
P3A/CCP3 input/output is mulitplexed with RC6. |
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CCP3MX = PORTB5 |
0xFF |
P3A/CCP3 input/output is multiplexed with RB5. |
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HFOFST -- HFINTOSC Fast Start-up |
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HFOFST = OFF |
0xF7 |
HFINTOSC output and ready status are delayed by the oscillator stable status. |
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HFOFST = ON |
0xFF |
HFINTOSC output and ready status are not delayed by the oscillator stable status. |
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T3CMX -- Timer3 Clock input mux bit |
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T3CMX = PORTB5 |
0xEF |
T3CKI is on RB5. |
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T3CMX = PORTC0 |
0xFF |
T3CKI is on RC0. |
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P2BMX -- ECCP2 B output mux bit |
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P2BMX = PORTC0 |
0xDF |
P2B is on RC0. |
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P2BMX = PORTB5 |
0xFF |
P2B is on RB5. |
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MCLRE -- MCLR Pin Enable bit |
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MCLRE = INTMCLR |
0x7F |
RE3 input pin enabled; MCLR disabled. |
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MCLRE = EXTMCLR |
0xFF |
MCLR pin enabled, RE3 input pin disabled. |
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CONFIG4L (address:0x300006, mask:0x85) |
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STVREN -- Stack Full/Underflow Reset Enable bit |
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STVREN = OFF |
0xFE |
Stack full/underflow will not cause Reset. |
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STVREN = ON |
0xFF |
Stack full/underflow will cause Reset. |
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LVP -- Single-Supply ICSP Enable bit |
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LVP = OFF |
0xFB |
Single-Supply ICSP disabled. |
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LVP = ON |
0xFF |
Single-Supply ICSP enabled if MCLRE is also 1. |
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XINST -- Extended Instruction Set Enable bit |
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XINST = OFF |
0xBF |
Instruction set extension and Indexed Addressing mode disabled (Legacy mode). |
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XINST = ON |
0xFF |
Instruction set extension and Indexed Addressing mode enabled. |
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DEBUG -- Background Debug |
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DEBUG = ON |
0x7F |
Enabled. |
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DEBUG = OFF |
0xFF |
Disabled. |
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CONFIG5L (address:0x300008, mask:0x0F) |
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CP0 -- Code Protection Block 0 |
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CP0 = ON |
0xFE |
Block 0 (000800-003FFFh) code-protected. |
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CP0 = OFF |
0xFF |
Block 0 (000800-003FFFh) not code-protected. |
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CP1 -- Code Protection Block 1 |
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CP1 = ON |
0xFD |
Block 1 (004000-007FFFh) code-protected. |
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CP1 = OFF |
0xFF |
Block 1 (004000-007FFFh) not code-protected. |
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CP2 -- Code Protection Block 2 |
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CP2 = ON |
0xFB |
Block 2 (008000-00BFFFh) code-protected. |
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CP2 = OFF |
0xFF |
Block 2 (008000-00BFFFh) not code-protected. |
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CP3 -- Code Protection Block 3 |
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CP3 = ON |
0xF7 |
Block 3 (00C000-00FFFFh) code-protected. |
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CP3 = OFF |
0xFF |
Block 3 (00C000-00FFFFh) not code-protected. |
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CONFIG5H (address:0x300009, mask:0xC0) |
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CPB -- Boot Block Code Protection bit |
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CPB = ON |
0xBF |
Boot block (000000-0007FFh) code-protected. |
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CPB = OFF |
0xFF |
Boot block (000000-0007FFh) not code-protected. |
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CPD -- Data EEPROM Code Protection bit |
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CPD = ON |
0x7F |
Data EEPROM code-protected. |
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CPD = OFF |
0xFF |
Data EEPROM not code-protected. |
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CONFIG6L (address:0x30000A, mask:0x0F) |
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WRT0 -- Write Protection Block 0 |
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WRT0 = ON |
0xFE |
Block 0 (000800-003FFFh) write-protected. |
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WRT0 = OFF |
0xFF |
Block 0 (000800-003FFFh) not write-protected. |
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WRT1 -- Write Protection Block 1 |
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WRT1 = ON |
0xFD |
Block 1 (004000-007FFFh) write-protected. |
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WRT1 = OFF |
0xFF |
Block 1 (004000-007FFFh) not write-protected. |
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WRT2 -- Write Protection Block 2 |
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WRT2 = ON |
0xFB |
Block 2 (008000-00BFFFh) write-protected. |
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WRT2 = OFF |
0xFF |
Block 2 (008000-00BFFFh) not write-protected. |
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WRT3 -- Write Protection Block 3 |
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WRT3 = ON |
0xF7 |
Block 3 (00C000-00FFFFh) write-protected. |
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WRT3 = OFF |
0xFF |
Block 3 (00C000-00FFFFh) not write-protected. |
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CONFIG6H (address:0x30000B, mask:0xE0) |
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WRTC -- Configuration Register Write Protection bit |
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WRTC = ON |
0xDF |
Configuration registers (300000-3000FFh) write-protected. |
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WRTC = OFF |
0xFF |
Configuration registers (300000-3000FFh) not write-protected. |
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WRTB -- Boot Block Write Protection bit |
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WRTB = ON |
0xBF |
Boot Block (000000-0007FFh) write-protected. |
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WRTB = OFF |
0xFF |
Boot Block (000000-0007FFh) not write-protected. |
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WRTD -- Data EEPROM Write Protection bit |
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WRTD = ON |
0x7F |
Data EEPROM write-protected. |
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WRTD = OFF |
0xFF |
Data EEPROM not write-protected. |
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CONFIG7L (address:0x30000C, mask:0x0F) |
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EBTR0 -- Table Read Protection Block 0 |
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EBTR0 = ON |
0xFE |
Block 0 (000800-003FFFh) protected from table reads executed in other blocks. |
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EBTR0 = OFF |
0xFF |
Block 0 (000800-003FFFh) not protected from table reads executed in other blocks. |
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EBTR1 -- Table Read Protection Block 1 |
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EBTR1 = ON |
0xFD |
Block 1 (004000-007FFFh) protected from table reads executed in other blocks. |
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EBTR1 = OFF |
0xFF |
Block 1 (004000-007FFFh) not protected from table reads executed in other blocks. |
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EBTR2 -- Table Read Protection Block 2 |
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EBTR2 = ON |
0xFB |
Block 2 (008000-00BFFFh) protected from table reads executed in other blocks. |
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EBTR2 = OFF |
0xFF |
Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks. |
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EBTR3 -- Table Read Protection Block 3 |
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EBTR3 = ON |
0xF7 |
Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks. |
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EBTR3 = OFF |
0xFF |
Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks. |
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CONFIG7H (address:0x30000D, mask:0x40) |
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EBTRB -- Boot Block Table Read Protection bit |
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EBTRB = ON |
0xBF |
Boot Block (000000-0007FFh) protected from table reads executed in other blocks. |
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EBTRB = OFF |
0xFF |
Boot Block (000000-0007FFh) not protected from table reads executed in other blocks. |
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