module Logic_builtin_used: sig .. end
sig
end
val add : Cil_types.logic_info -> unit
Cil_types.logic_info -> unit
val mem : Cil_types.logic_info -> bool
Cil_types.logic_info -> bool
val iter : (Cil_types.logic_info -> unit) -> unit
(Cil_types.logic_info -> unit) -> unit
val self : State.t
State.t